The semiconductor integrated circuit industry has experienced rapid growth in the past several decades. Technological advances in semiconductor materials and design have produced increasingly smaller and more complex circuits. These material and design advances have been made possible as the technologies related to processing and manufacturing have also undergone technical advances. In the course of semiconductor evolution, the number of interconnected devices per unit of area has increased as the size of the smallest component that can be reliably created has decreased.
The pursuit of smaller feature size has required a number of technological changes, including changes in the control of fabrication processes. In a semiconductor fabrication facility, often referred to as a “fab,” monitoring the results of process steps has become even more critical. Misalignment, lithography defects, and tool drift can result in a process generating unsatisfactory results even after a period of time with satisfactory results. In order to monitor and control the various processes performed in semiconductor device fabrication, techniques have been developed including reliance on comparing wafers in terms of mean, 3-sigma, maximum, and/or minimum differences. While the techniques have provided certain benefits in semiconductor process control to date, they have not been entirely satisfactory.
Aspects of the figures in the present disclosure are best understood from the following detailed description when read in connection with the figures.